1. Field
Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to analog-to-digital converters.
2. Description of the Related Technology
In certain electronic devices, analog-to-digital converters (ADCs) are used for converting an analog signal into a digital format. Examples of such electronic devices include, but are not limited to, imaging devices, communication devices, and display devices.
An analog-to-digital converter (ADC) can use one of several architectures, such as serial architecture, delta-sigma architecture, and pipelined architecture. Among the ADC architectures, the pipelined architecture is widely used in applications, such as video imaging systems, digital subscriber loops, Ethernet transceivers, and wireless communications. The pipelined ADC is also known as a sub-ranging ADC.
Referring to FIG. 1A, one example of a conventional pipelined analog-to-digital converter (ADC) will be described below. The illustrated pipelined ADC 100 includes first to N-th multiplying digital-to-analog converter (MDAC) stages 110-140 coupled in cascade, and a control and correction logic 150.
The first MDAC stage 110 receives an analog input signal VIN, and generates a first n-bit digital signal D1 that forms the most significant bits (MSB) of a resulting digital output signal DOUT. The first MDAC stage 110 also outputs a first residue analog signal V1 to the second stage 120. Similarly, the second MDAC stage 120 receives the first residue analog signal V1, and generates a second n-bit digital signal D2 that forms the second most significant bits (MSB) of the digital output signal DOUT. The second MDAC stage 120 also outputs a second residue analog signal V2 to the next stage.
Likewise, the i-th MDAC stage 130 receives a residue analog signal Vi-1 from an immediately preceding stage, and generates an i-th n-bit digital signal Di that forms part of the digital output signal DOUT. The i-th MDAC stage 130 also outputs an i-th residue analog signal Vi to the next stage. The last and N-th MDAC stage 140 receives a residue analog signal VN-1 from an immediately preceding stage, and generates an N-th n-bit digital signal DN that forms the least significant bit (LSB) of the digital output signal DOUT.
Referring to FIG. 1B, one example of the configuration of an MDAC stage of the pipelined ADC 100 of FIG. 1A will be described below. The illustrated stage is the i-th stage 130 of FIG. 1A. A skilled artisan will, however, appreciate that the other MDAC stages of the pipelined ADC 100 of FIG. 1A can have the same or similar configuration.
The MDAC stage 130 includes an analog-to-digital converter (ADC) 132, a digital-to-analog converter (DAC) 134, a summation block 136, and an amplifier 138. The ADC 132 converts the (i−1)-th residue analog signal Vi-1 from the immediately preceding stage into the i-th n-bit digital signal Di. The DAC 134 converts the i-th n-bit digital signal Di into an analog signal Ai corresponding to the digital signal Di. The summation block 136 subtracts the analog signal Ai from the residue analog signal Vi-1, and provides a resulting signal to the amplifier 138. The amplifier 138 amplifies the resulting signal by a gain Gi to output the i-th residue signal to the next stage. The ADC 132, the DAC 134, the summation block 136, and the amplifier 138 can be implemented as a circuit block to form an MDAC.
Referring now to FIG. 2A, one example of a circuit that can form a stage of the pipelined ADC 100 of FIG. 1A will be described below. For clarity, the case of 1-bit is described, and a comparator is used for the ADC 210. However, in practical circuits, multiple bits are used. The illustrated circuit 200 includes a 1-bit flash ADC 210, a capacitor block 220, an amplifier 230, an amplifier capacitor Camp, a first switch SW1, an output switch SW0, and first to fifth nodes N1-N5.
The 1-bit flash ADC 210 serves to quantize an input analog voltage Vin (or a residue analog voltage from an immediately preceding stage) to one bit. The flash ADC 210 includes a voltage comparator 212 that includes a non-inverting input 212a, an inverting input 212b, and an output 212c. The non-inverting input 212a is coupled to the first node N1 configured to receive the input analog voltage Vin. The inverting input 212b is coupled to a voltage reference, ground in the illustrated example. In a practical ADC 210, multiple comparators are present, and each can be coupled to a separate reference voltage. The output 212c is coupled to the fourth node N4, and is configured to output a digital output signal Do. The fourth node N4 is coupled to the control and correction logic 150 (FIG. 1A) and the capacitor block 220.
The capacitor block 220 includes a second switch SW2, a first reference switch rsw1, a second reference switch rsw2, and a capacitor C1. The second switch SW2 is coupled between the first node N1 and the fifth node N5, and switches on or off at least partly in response to an analog-to-digital converter (ADC) clock signal ADC CLK. Operation of these switches will be described later.
The first reference switch rsw1 is coupled between the fifth node N5 and a first reference voltage source VREF1. The first reference voltage source VREF1 can have a voltage value of +VFS/2, where VFS represents a positive full-swing voltage value. The second reference switch rsw2 is coupled between the fifth node N5, and a second reference voltage source VREF2 having a voltage value of −VFS/2. The first and second reference switches rsw1, rsw2 switch on or off at least partly in response to the digital output signal Do. Operation of these switches will be described later. The capacitor C1 is coupled between the fifth node N5 and the second node N2.
The amplifier 230 includes an inverting input coupled to the second node N2, a non-inverting input coupled to ground, and an output coupled to the third node N3. The amplifier capacitor Camp includes a first terminal coupled to the second node N2, and a second terminal coupled to the third node N3.
The first switch SW1 is coupled between the second node N2 and ground, and switches on (low resistance) or off (high resistance) at least partly in response to the ADC clock signal ADC CLK. The output switch SW0 is coupled between the third node N3 and ground.
During a first phase (which may be referred to as “sample phase”) of the operation of the circuit 200 (for example, while the clock signal ADC CLK is low), the input analog voltage Vin is sampled across the capacitor C1 by switching on the first and second switches SW1, SW2, and the output switch SW0. The reference switches rsw1, rsw2 are turned off. During this phase, the comparator 212 is in a tracking mode.
During a second phase (which may be referred to as “hold phase”) of the operation of the circuit 200 (for example, while the clock signal ADC CLK is high), the first and second switches SW1, SW2, and the output switch SW0 are switched off. During this phase, the comparator 212 is in a latch mode in which it determines whether the input analog voltage Vin is greater than the reference voltage, and outputs the digital output signal Do, based on the determination. In addition, an appropriate reference voltage, either +VFS/2 or −VFS/2, is applied to the capacitor C1 through either of the first and second reference switches rsw1, rsw2, depending on the digital output signal Do. The input voltage, Vin, is subtracted from either +VFS/2 or −VFS/2, depending on the output signal Do, and that difference charge is transferred to the amplifier capacitor Camp by the fact that the second node N2 is at virtual ground (due to the high open loop gain of the amplifier 230). The relationship between the input voltage Vin and the output voltage Vout is shown in FIG. 2B.
In general, the comparator 212 of FIG. 2A may include a pre-amplifier 310 and a latch 320, as shown in FIG. 3A. The pre-amplifier 310 serves to amplify the input analog voltage Vin and provide the amplified input analog voltage to the latch 320. The latch 320 receives the amplified difference between the input analog voltage Vin and a reference voltage, for example, 0V in the illustration. When a clock CLK provided to the latch 320 is high, the positive feedback of the latch 320 is suppressed by a first latch switch, for example, LTR1 in FIG. 3B. When the clock goes low, the first latch switch LTR1 turns off, and the positive feedback of the latch 320 takes the received difference voltage, and gains it up until one output goes to ground (logic 0) and the other to the supply (logic 1).
Referring now to FIG. 3B, one example of a circuit for the comparator 212 of FIG. 2A will be described below. The illustrated circuit 300 includes a pre-amplifier 310, a latch 320, and a current mirror 330.
The pre-amplifier 310 can include a first amplifier transistor ATR1, a second amplifier transistor ATR2, and a current source CS. The first amplifier transistor ATR1 includes a drain coupled to the current mirror 330, a source coupled to the current source CS, and a gate configured to receive one of the input analog voltage Vin and the reference voltage. The second amplifier transistor ATR2 includes a drain coupled to the current mirror 330, a source coupled to the current source CS, and a gate configured to receive the other of the input analog voltage Vin and the reference voltage. The current source CS is configured to generate a current flowing from the sources of the transistors ATR1, ATR2 to ground.
The latch 320 includes first to third latch transistors LTR1-LTR3, and first and second latch nodes LN1, LN2. The first latch transistor LTR1 includes a source/drain coupled to the first latch node LN1, a drain/source coupled to the second latch node LN2, and a gate configured to receive a clock signal CLK. The second latch transistor LTR2 includes a source/drain coupled to the first latch node LN1, a drain/source coupled to ground, and a gate coupled to the second latch node LN2. The third latch transistor LTR3 includes a source/drain coupled to the second latch node LN2, a drain/source coupled to ground, and a gate coupled to the first latch node LN1. The first and second latch nodes LN1, LN2 are configured to receive first and second current signals i1 and i2, respectively, from the current mirror 330.
The current mirror 330 serves to copy currents from the pre-amplifier 310, and provide the copied currents to the latch 320. A skilled artisan will appreciate that various configurations of current mirrors can be adapted for the current mirror 330.
During operation, each of the gates of the first and second amplifier transistors ATR1, ATR2 receives a respective one of the input analog voltage Vin and the reference voltage. Depending on the levels of the input analog voltage Vin and the reference voltage, the first and second amplifier transistors ATR1, ATR2 allow first and second amplifier currents ia1, ia2 to flow therethrough. The first and second amplifier currents ia1, ia2 are copied by the current mirror 330, and are provided to the latch 320 as first and second current signals i1, i2.
During a first phase of the operation of the comparator 212, the clock signal CLK is high. The first latch transistor LTR1 thus connects the first latch node LN1 to the second latch node LN2 so that the positive resistance of the LTR1 is lower in resistance than the magnitude of the negative resistance of the second and third latch transistors LTR2 and LTR3, thus keeping the latch 320 from regenerating. Some amount of the difference between the input signal Vin and the comparator reference will be seen across the first and second latch nodes LN1, LN2 by the currents i1 and i2.
During a second phase of the operation, the clock signal CLK goes low, and thus the first latch transistor LTR1 is turned off, disconnecting the first latch node LN1 from the second latch node LN2, thus allowing the difference signal to be exposed to the positive feedback of the latch 320. For example, when the first current signal i1 is greater than the bias current Ib, and the second current signal i2 is less than the bias current Ib, a transition is initiated to force the second latch transistor LTR2 to be in an “OFF” state, while the third transistor M3 remains in an “ON” state. It, however, takes some time (which is so-called “regeneration time”) for the nodes LN1, LN2 to transition to a new steady state that is indicative of which one of the first and second current signals i1 and i2 is greater than the other. The smaller the voltage between the first and second latch nodes LN1 and LN2, the longer it takes for regeneration (the relationship between the difference in voltage between the first and second latch nodes LN1 and LN2 and the regeneration time is exponential). When the voltage is so small between the first and second latch nodes LN1 and LN2 that the latch 320 does not regenerate in the appropriate amount of time, the latch 320 is said to be in a meta-stable state, meaning that neither output VOUT or VOUTb has reached a valid logic level.